Thin-film transistor liquid-crystal display (TFT-LCD) is a flat-panel display device that displays images by an array of liquid-crystal pixels. As shown in FIG. 1, a typical TFT-LCD display panel 10 comprises a display module 20 having a plurality of pixels 21 arranged in a two-dimensional array. These pixels are controlled by a plurality of data lines D1, D2, . . . , Dn and a plurality of gate lines G1, G2, . . . , Gm. The data lines are connected to a data source driver 30 and the gate lines are connected to a gate line driver 40. A printed circuit board (PCB) 50 containing circuits necessary to convert image data into voltage signals is connected to drivers 30 and 40 via a control bus 52.
In recent years, amorphous silicon gate drivers (ASGDs), which are integrated circuits (ICs) directly fabricated on the same substrate that supports the pixel array, are replacing silicon-chip gate driver ICs for gate line driving of the LCD display. The ASGD technology allows for fewer external components, thus reducing the cost of manufacturing.
As shown in FIG. 2a , an exemplary ASGD gate line driving circuit contains a shift register module 100 that has a plurality of shift registers 110. Each shift register (SR) 110 has an input terminal (In), an output terminal (Out), a voltage source terminal (Vs), a first clock signal terminal (Ck1) and a second clock signal terminal (Ck2). Signals coming from the control bus 52 (see FIG. 1) for gate line driving include a negative voltage Vss, a start pulse signal Vst, a clock signal Vck and a complementary clock signal xVck that has a 180° phase shift relative to the clock signal Vck. Vss is applied to the voltage source terminal Vs of each SR. Vst is applied to the input terminal of the first SR in the SR module. Vck and xVck are applied to clock terminals Ck1 and Ck2, respectively, of each SR in an alternate fashion such that Vck is applied to Ck1 and xVck is applied to Ck2 in every odd-numbered SR, whereas xVck is applied to Ck1 and Vck is applied to Ck2 in every even-numbered SR.
The output terminal of an SR connects to a gate line of the LCD array. Each gate line connects to one row of pixels. A positive output pulse from the SR provides a signal to the gate line in order to energize the pixels in the corresponding row.
The SRs in the SR module are connected in a cascaded manner. When a pulse Vst indicating the beginning of a frame arrives at the first shift register SR001, SR001 provides an output pulse on the first gate line, Gateline001, in correspondence to a clock signal Vck. The same output pulse also arrives at the input terminal of the second shift register SR002 so as to cause SR002 to provide an output pulse on the second gate line, Gateline002, in correspondence to the clock signal xVck. The output pulse from SR002 also arrives at the input terminal of the third shift register SR003 so as to cause SR003 to provide an output pulse on the third gate line, Gateline003, in response to the clock signal Vck. In this manner, every gate line receives a positive pulse in sequence. The odd-numbered SRs are operated in synchronization with the clock signal Vck, whereas the even-numbered SRs are operated in synchronization with the clock signal xVck. A time sequence of Vck, xVck, Vst and SR outputs is shown in FIG. 2b. 
In an active-matrix TFT-LCD, the TFT switching element in a pixel only needs to be in an “ON” state (for charging the capacitors that maintain a voltage between the pixel electrodes) for a fraction of time associated with a frame. For the remainder of the time of the frame, it is in an “OFF” state. Thus, in a typical SR for gate line driving, a pull-up TFT is used to provide a short positive pulse at the SR output to turn on the TFT switching element in the pixel. The drain and the gate of the pull-up TFT are usually connected through a capacitor. A pull-down TFT is connected in series to the source of the pull-up TFT to keep the output of the SR in a negative voltage state after the positive pulse is provided. The source terminal of the pull-down TFT is connected to a negative voltage source Vss. Except for the time when the pull-up TFT produces the positive pulse, the gate of the pull-down TFT is maintained at an “ON” state in order to keep the pull-down TFT in a conducting state. At a same time, a TFT is connected to the gate of the pull-up TFT to discharge the capacitor and to keep the gate of the pull-up TFT at the Vss voltage level after the positive pulse is generated and before the input pulse is received.
Jeon et al. (U.S. Pat. No. 6,690,347 B1) and Moon (U.S. Patent Application Publication No. 2004/0046729 A1) disclose a shifter register circuit wherein a pull-down driving section comprising of two TFTs connected in series between a positive voltage source Vdd and a negative voltage source Vss to control the gate voltage of the pull-down TFT. In Jeon et al. and Moon, the input of an SR is connected to the output of a preceding SR. Moon et al. (U.S. Pat. No. 6,845,140 B2) discloses a shift register circuit wherein a carry buffer is used to generate a carry signal for providing a positive pulse to the input of the following SR. In Jeon et al., Moon and Moon et al., when the pull-up TFT is not providing a positive pulse, the gate of the pull-down TFT is maintained at a positive voltage level provided by a positive voltage source Vdd.
It is known in the art that, in ASGDs, the switching threshold of an amorphous-silicon TFT may drift if a constant voltage is applied to the gate terminal for a long period of time. This drift is also known as floating. When the applied voltage to the gate is positive, the threshold drifts higher. When the applied voltage is negative, the threshold drifts lower. The threshold drift may reduce the charge flow in the TFT, affecting its normal operations. For that reason, two complementary pull-down modules are alternately used to provide two complementary pulse signals to the gate of the pull-down TFT, as shown in FIG. 3.
In the Nth shift register 110 as shown in FIG. 3, Q2 is the pull-up TFT, and Q1 is for driving Q2. The gate and the drain of Q1 are connected to the input of the SR for receiving a positive pulse from the output of the preceding SR (N-1). The source of the driving TFT Q1 is connected to the gate of Q2. The drain of Q2 is connected to Ck1 for receiving a clock signal. The source terminal of Q2 is connected to the output terminal of the shift register 100 for providing a positive output pulse in response to the input pulse and the clock signal at Ck1. The source of Q2 is also connected to two pull-down TFTs Q3 and Q9 so as to keep the output in a negative voltage state after the output pulse is produced. As shown in FIG. 3, Q9 is in the first pull-down module and Q3 is in the second pull-down module. The gate of Q2 is also connected to two pull-down TFTs Q6 and Q10 so as to keep the gate terminal of Q2 in a negative voltage state after the pulse is generated at the output terminal and before the pulse from the preceding SR is received. As shown in FIG. 3, Q10 is in the first pull-down module and Q6 is in the second pull-down module.
The two pull-down modules are operated in a cooperative manner so that each module carries out the pull-down task approximately 50% of the time. The gates of Q9 and Q10 in the first pull-down module receive clock pulses of 50% duty cycle from a first pulse source, which comprises a pair of TFTs Q12 and Q13 connected in series. The gates of Q3 and Q6 in the second pull-down module receive complementary clock pulses from a second pulse source, which comprises a pair of TFTs Q4 and Q5 connected in series. As shown in FIG. 3, the drain and the gate of Q12 in the first pulse source are connected to Ck1, and the drain and the gate of Q4 in the second pulse source are connected to Ck2. The source terminals of Q13 and Q5 are connected to Vss. The gate of Q13 is connected to Ck2, and the gate of Q5 is connected to Ck1.
The source terminal of Q12 is also connected to a first pulse suppression TFT Q11 to keep the gates of Q9 and Q10 in a negative voltage state, and the source terminal of Q4 is connected to a second pulse suppression TFT Q7 to keep the gates of Q6 and Q3 in a negative voltage state when the output of the SR is high. In addition, the source terminal of Q4 is connected to a third pulse suppression TFT Q8 to keep the gates of Q6 and Q3 in a negative voltage state when the input of the SR is high. The source terminals of Q6, Q7, Q8, Q9, Q10 and Q11 are all connected to Vss at the terminal VS.
The clock signal at Ck1 in the Nth SR is Vck if N is odd, and is xVck if N is even. The clock signal at Ck2 is complementary to the clock signal at Ck1 in phase. The relationship of the state of the Vck, xVck is shown in FIG. 4. Thus, when the voltage level at Ck2 is low, the voltage level at the gates of Q9 and Q10 is substantially equal to VH (except when the output of SR is high), and the voltage level at the gates of Q3 and Q6 is substantially equal to Vss. Likewise, when the voltage level at Ck2 is high, the voltage level at the gates of Q9 and Q10 is substantially equal to Vss, and the voltage level at the gates of Q3 and Q6 is substantially equal to VH (except when the input and/or output of the SR is high).
The gates of Q3, Q6, Q9 and Q10 are at VH approximately 50% of the time and at Vss proximately 50% of the time. When the voltage level is high (VH), the threshold drift in the Q3, Q6, Q9 and Q10 increases. When the voltage level is low (Vss), the threshold drift in the Q3, Q6, Q9 and Q10 decreases. If the increase in the threshold drift and the decrease in the threshold drift are equal, then the net threshold drift is substantially zero. The operations of the SR are said to be stable.
However, VH is approximately equal to +18V and Vss is approximately equal to −6V. As a result, the threshold drift in pull-down TFTs Q3, Q6, Q9 and Q10 increases with time. This increase may affect the instability of the pull-down modules and the SR as a whole.